Advances in semiconductor manufacturing processes, digital system architecture, and wireless infrastructure, among other things, have resulted in a vast array of electronic products, particularly consumer products, that drive demand for ever-increasing performance and density in non-volatile memory.
One means of increasing the performance and density of non-volatile memories such as flash memory, is to shrink the dimensions of floating gate transistors that are used in flash memories. It is well-recognized that shrinking the physical dimensions of the floating gate transistor also reduces the size of the floating gate itself and thus reduces the amount of charge that can be stored. When less charge storage is available, the memory cell becomes more sensitive to memory operations that unintentionally inject or remove charge, and thereby degrade the ability to store data successfully over many operational cycles. Mechanisms, other than erasing and programming, that affect the amount of charge stored on the floating gate of a flash memory cell include word line disturb error and bit line disturb error.
Word line and bit line disturb errors are similar to each other in that the voltages that appear across the terminals of a flash memory cell, i.e., across the terminals of a floating gate transistor, are such that electrons are caused to tunnel out of the floating gate, and typically into the drain. This unintended electron tunneling causes a shift in the threshold voltage of the floating gate transistor, and consequently may change the data previously stored. This data degradation phenomenon occurs in a memory cell that has not been selected, but which shares a word-line and/or bit-line with one or more memory cells that have been selected for an erase operation.
In order to overcome the loss of data integrity caused by these unintended increases or decreases in stored charge, refresh operations have been used in flash memories. Refresh operations read out data from a section of the flash memory array and re-program the corresponding memory cells with the same data.
Various schemes for refreshing the content of flash memory cells that are affected by word-line or bit-line disturb errors have been implemented in the past. Unfortunately, conventional refresh schemes that refresh all potentially affected memory cells at the same time, consume undesirable amounts of time and resources.
It is noted that the cross-sectional representations of various semiconductor structures shown in the figures are not necessarily drawn to scale, but rather, as is the practice in this field, drawn to promote a clear understanding of the structures, process steps, and operations which they are illustrating.